1. Field of the Invention
The invention relates generally to flash based devices and more particularly to systems and methods for efficient programming and erasing of such devices.
2. Background of the Invention
Flash based devices, such as flash based memory devices, comprise a plurality of cells that can be electrically programmed and erased. Each cell represents a bit of information and are typically arranged into words, where each word comprises a certain number of bits. Each cell also typically comprises one or more transistors. In order to reduce the overall size of a flash based circuit, single transistor cells are often preferred. One well known type of single transistor cell used in conventional flash based devices makes use of a single transistor with a special construction known as a floating gate construction, and is referred to as a floating gate transistor.
FIG. 1A is a diagram illustrating a floating gate transistor 100. As can be seen, floating gate transistor 100 comprises a stacked gate configuration above a silicon substrate 118. The stacked gate configuration comprises a control gate 102 stacked above a floating gate 104, which is in turn above the silicon substrate 118. The gates 102 and 104 are often constructed from polysilicon material and are separated by oxide layers (not shown). A drain (D) region 108 and source (S) region 106 are then formed within a well 112 in silicon substrate 118. It will be understood that the drain 108 and source 106 regions are of opposite doping relative to well 112. For example, if drain 108 and source 106 are N-type regions, then well 112 will be a P-type region. In triple well configurations, a second well surrounding well 112 can also be included in silicon substrate 118. The region of silicon substrate 118 below floating gate 104 is referred to as the channel region, or channel 110.
FIG. 1B is a schematic diagram depicting the schematic equivalent of floating gate transistor 100. As can be seen, for various operations control gate 116 is coupled with a Word Line (WL) voltage 116, and drain 108 is coupled with a Bit Line (BL) voltage 114. Source 116 is then often coupled to ground as explained below.
There are three main operation performed on a flash cell, e.g., comprising a floating gate transistor 100. These operations are read, write, and erase. The write operation can also be referred to as a programming operation. Typically, a Flash based device, i.e., a flash memory device, is erased and then programmed with instructions or code. In operation, the code is then accessed and read by a device such as a processor.
A cell is programmed by applying a relatively high programming voltage to control gate 102 and a lower voltage to drain 108. For example, conventional device often use a control gate voltage 116 of 9-10 volts and a drain voltage 114 of 5 volts during programming. The source voltage is typically maintained at ground, or 0 volts. The programming voltages are configured to create a relatively high voltage potential between drain 108 and source 106, which causes electrons to flow from source 106 to drain 108 through channel 110. Additionally, the relatively high voltage applied to control gate 102 raises the voltage potential of floating gate 104. This high potential attracts electrons flowing through channel 110, causing them to “tunnel” through the oxide layer (not shown) separating floating gate 104 from silicon substrate 118. This phenomenon is often referred to as hot carrier injection.
A successful programming operation results in injection of enough electrons onto floating gate 104 to achieve a desired threshold voltage (Vt) for flash cell 100. The threshold voltage (Vt) is the voltage that must be applied to control gate 102 to cause conduction through channel 110 during a read operation.
Upon removal of the programming voltages, the injected electrons are trapped on floating gate 104, creating a negative voltage that must be overcome in order to effect a read. The threshold voltage (Vt) needed to overcome the negative effect of the injected electrons can for example be 4 volts; however, The threshold voltage (Vt) can vary by implementation, Moreover, as discussed below, the threshold voltage (Vt) can vary by cell due to process variations.
A cell 100 is read by applying a voltage 116 to control gate 102, and a lower voltage 114 to drain 108, while grounding source 106. For example, a voltage of 5 volts can be applied to control gate 102 and a voltage of 1 volt to drain 108. Current on the bit line (BL) is then sensed to determine whether cell 100 is programmed. If cell 100 is programmed and the threshold voltage (Vt) is relatively high, e.g., 4 volts, then the bit line (BL) current will be approximately 0 amps. If the cell is not programmed and the threshold voltage is relatively low, e.g., 2 volts, then the control gate voltage 116 will enhance channel 110 and the BL current will be relatively high.
A cell 100 can be erased by applying a high voltage to source 106, a lower voltage to control gate 102, and allowing drain 108 to float. For example, a voltage of 12 volts can be applied to source 106, while control gate 102 is grounded, or a lower voltage, such as 5 volts can be applied to source 106, while a negative voltage, such as 10 volts, is applied to control gate 102. This causes the electrons injected onto floating gate 104 to undergo a phenomenon known as Fowler-Nordheim tunneling from floating gate 104, through the oxide layer (not shown) separating floating gate 104 from silicon substrate 118, and to source 106. In addition, channel 110 is also erased by letting drain 108 and source 106 float and applying an erase voltage to control gate 102.
A problem with conventional flash based devices is that the manufacturing variances can cause some cells to become “over-erased” before other cells are sufficiently erased. In over-erased cells, floating gate 104 has a very low negative charge, or even a positive charge. An over-erased cell can act as a depletion mode transistor that cannot be turned off by normal operating voltages. Thus, an over-erased cell will have an associated leakage current that can prevent accurate reads of not just the over-erased cell, but other cells coupled with the same BL. To combat this problem, a process referred to as soft-programming can be implement to correct for over-erased cells; however, conventional soft programming techniques can be inefficient because voltage 116 that can be applied to the WL during soft programming is limited. A higher voltage 116 would increase the efficiency of soft programming, but too high a voltage can cause an over soft programming condition.
Further, if the over-erase condition for a given cell is severe, it can require more current to correct than can be supported. Because many cells are often soft programmed at the same time, the current required can vary significantly depending on how many cells are over-erased. This can make it difficult to predict how much current will be needed. In fact, the current required can be so great that it exceeds what can be supplied by the charge pump coupled with the drain during soft programming.